CMO High-Frequency Switched-Capacitor Filters for Telecommunication Applications

A digitally programmable high-frequency switched-capacitor filter for use in Switched Digital Video (SDV/VDSL) link is described. The highest available clock frequency in the system is 51.84MHz (fs = 2f sub (clock) = 103.68MHz for double-sampling) while the three desired low-pass corner frequencies (f sub c) are 8,, 12, and 20MHz. The double-sampling, Bilinear, Elliptic, fifth-order switched-capacitor filter meets the desired -40dB attenuation at 1.3 f sub c, and -30dB at 1.25 f sub c. For the 12MHz corner frequency setting, given the 2 V sub (pp) differential input, the measured worst case THD is -60dB, and SNR of 54dB. The analog power dissipation is 125mW from a 5V power supply. The test results indicate that the clock frequency can be increased to 73MHz without any ill-effects. More measurements verify that an all-digital CMOS implementation, utilizing metal-sandwich capacitors, performs as well as the special-layer analog capacitors implementation, with a small reduction in the absolute corner frequencies. The prototype ICs are fabricated in a 0.35 micron 5V (0.48 micron drawn) CMOS process.