Experiments in Logic Optimization

We have conducted a number of experiments, gathering over 5000 data points, to answer several important questions about logic synthesis and its application to hardware design: Are the results of logic synthesis competitive with manual design? How do various logic optimization algorithms and heuristics compare with one another? What is the cost- benefit ratio of these methods? Can we use inexpensive logic optimization methods to estimate the results of more powerful methods? Can technology- independent literal counts be used to estimate the area of standard cell designs? We have performed experiments on 93 public and industrial design examples using the MIS and BOLD logic synthesis systems. Our experiments show that: logic synthesis is competitive with manual design; stronger optimization methods give somewhat better results (10% - 30%) at much greater computational cost (2X and more); simple logic synthesis methods can be used to estimate the results of the more powerful, costly methods and, for our standard cell library and technology mapper, literals are a good estimate of area before routing.