Experiments Using Automatic Physical Design Techniques for Optimizing Circuit Performance

Recently there have been papers by Hedlund, Marple, Matson, Obermier and Ruhli on numerical techniques for transistor width optimization. These numerical techniques have been applied to circuits with up to few hundred transistors. Previously we have shown a posynomial programming approach to transistor sizing. (Posynomials behave like convex functions.) 

This program couples a static timing analyzer to transistor sizing procedures. The TILOS program, which implements the posynomial program, has been shown, both theoretically and experimentally, to have a complexity proportional to the number of transistors. This low complexity has enabled the TILOS program to size static synchronous CMOS circuits with as many as 40K transistors in a few hours of DEC VEX 8650 computer time.