Gate Technology Issues for Silicon MOS Nanotransistors

We report on progress and gate technology issues in scaling both NMOS and PMOS conventional planar transistors to a physical gate length of 30nm and an expected effective channel length of 10 nm. For this work, device fabrication employs direct write e-beam lithography to form a single lithography level ring structure capable of exploring the practical limits of gate processing. Other processing features include ultrathin gate dielectric formation (~0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. We demonstrate lithographically defined resist features as narrow as 28 nm, that were obtained with NEB 31, a negative tone chemically amplified resist. Electron energy loss spectroscopy is used to analyze the interface to the gate dielectric region to understand the limits of scaling of silicon dioxide. Scanning capacitance microscopy is shown to be useful in determining the effective channel lengths and source drain junction depths on cross-sectioned devices to calibrate process simulation programs and thereby optimize the transistor design. We present DC electrical results obtained for high performance NMOS and PMOS nanotransistors made using this process. Based on measured performance, simulations are presented which predict sub-threshold current for the NMOS transistors with gate lengths down to 26nm. These calculations can be used to both infer limits on large scale integration and also to estimate process latitude for CD control and edge roughness in the gate formation sequence of CMOS technology beyond 40 nm.