Hierarchical Interference Noise Analysis in Large VLSI Circuits though Reduced-Order Modeling of Noise Power Spectral Density Functions

The paper introduces a methodology and efficient computational techniques for the evaluation of the interference noise, caused by digital switching activity, in sensitive circuits of a mixed-digital-analog chip. The digital switching activity is modeled stochastically as functions defined on Markov chains. The actual interference signal is obtained through the modulation of the discrete stochastic signal with real current injection patterns stored a priori in a pre-characterized library. The interference noise results from the propagations of these continupus stochastic signals through the linear network that models the chip power grid, substrate and relevant package parasitics. The interference noise power spectral density is computed by linear frequency-domain analysis, which involves solving very large matrix systems. The Markov chain model also involves very large vectors and matrices, which are efficiently manipulated exploiting their special structure and efficient graph representations. The computation of spectral densities is done efficiently using reduced-order modeling techniques. The interference analysis of a large mixed-signal chip is enabled by the hierarchical application of the methodology, first to the circuit blocks that form it, then to the whole chip itself.