Hierarchical Scheduling System for Parallel Architectures.

Scheduling and resource allocation are important steps for implementing algorithms on parallel architectures. A way to perform these tasks using data-flow methods to implement digital signal processing algorithms is described. Special techniques allow an efficient implementation of loops and decision- structures. A tool under development makes interactive scheduling, resource allocation, simulation, and algorithm-architecture adaption possible. It works on various hierarchical levels and provides graphical representation of algorithms, architectures, and simulation results. A design example, implemented on a parallel modular signal processor, shows the method's efficiency.