High Density Interconnect for Advanced VLSI Packaging
24 March 1987
Currently, integrated circuits (IC) are individually packaged to provide protection from mechanical and environmental damage during testing, shipping, and use in electronic equipment. Common packages are the dual-in-line package (DIP), the pin grid array (PGA), and the chip carrier (CC). These packages, each containing a single IC, are usually attached to a printed wiring board (PWB). Conductors on the PWB provide the interconnects between the packaged chips. One of the functions of the package, in addition to providing protection for the chip, is to provide electrical fanout from the chip input/output (I/O) pads, typically on 8 mil centers, to the package leads which are usually on 100 mil centers. As a consequence, packages are much larger than the individual IC chips. As IC dimensions decrease and manufacturing techniques improve, IC functionally has increased at an exponential rate so that the performance of newer devices is often limited by the number of I/O's provided by the package. Another disadvantage of current packaging technology is the limitation in device performance caused by delays and inductances when chips are connected through the printed wiring board.