High-speed reduced-state sequence estimation

The processing speed of reduced-state sequence estimation (RSSE) is limited by a data dependent recursive loop which incorporates branch metric computation, survivor memory operations, and decision-feedback equalization in addition to the add-compare-select function. Thus parallel processing methods which have been developed to speed up the Viterbi algorithm cannot be applied to RSSE. In this paper techniques are developed which shorten the critical path of RSSE to make it suitable for the high-speed implementation in VLSI.