Interconnect modeling and signal integrity issue I

Summary form only given, as follows. As the interconnect delay dominates the gate delay in today's deep submicron design, the accurate and efficient modeling of interconnects becomes imperative to improve circuit performance and preserve signal integrity. This year, we have an excellent session on interconnect modeling and signal integrity issues, presented by world-renown experts in this area. In the first half of the session, researchers from UCLA will first present their analytic formula for the peak crosstalk noise and delay uncertainty due to coupling. Then researchers from the Stanford University will propose a relative-window method to quantify the crosstalk effect on delay degradation. The third paper, which is a joint work between the University of Rochester and IBM, will describe the effects of interconnect inductance on the repeater insertion algorithms. Finally, researchers from the Georgia Institute of Technology will demonstrate a striking 0. lum ASIC macrocell using optimal n-tier interconnect architecture.