LAMP: Automatic Test Generation for Asynchronous Digital Circuits

The automatic test generation system (ATG) was designed to provide fault-detection tests for single stuck-at faults in combinational and sequential circuits. Since this problem has essentially been solved for combinational circuits, 1-3 this paper concentrates on aspects of automatic test generation for sequential circuits. The ATG algorithms presented attempt to account for actual circuit behavior as closely as possible. Hence} it is necessary to create 1477 a computer model of the actual gates in the logic circuit. The circuit description used by ATG will utilize a unit/zero time-delay model, where a gate can assume one of three values: logical 0, logical 1, and don't-know X. This model has been widely used for logic-circuit simulation. 4 ' 5 Because the test-generation algorithms described use the same model as many simulators, there are parallels between the simulation and test-generation techniques. These result from the effort to increase the accuracy of test generation to achieve the accuracy of current simulation techniques. The major drawback of previous algorithms 6-8 for test generation for sequential circuits is the lack of a satisfactory model for the sequential circuit. Previous algorithms use either the Huffman model or an iterative combinational circuit model for sequential circuits. While these models are mathematically convenient, they are hardly accurate representations of real logic circuits. The system to be presented here has the following features: (i) Requires no identification of feedback lines.