Margin Considerations for an Esaki Diode Resistor OR Gate

* This work was supported in part by the U.S. Army Signal Corps under contract DA-36-039 sc-64618. 213 214 THE BELL SYSTEM TECHNICAL JOURNAL, JANUARY 19(51 BIAS Fig. I --Esaki diode-resistor logic. First, a general description of the system will be given (Section II), followed by a qualitative margin analysis (Section III).* In Section IV it is shown that the present system permits only a finite logical gain, even for zero margins and infinite switching time. The switching speed is analyzed in Section V, followed by the quantitative margin analysis (Section VI). The final result of the quantitative margin analysis is brought into a form corresponding to the qualitative analysis, which permits the reader to follow the discussion (Section VII) and the conclusion (Section VIII) without studying in detail the reasoning in Sections V and VI. The basic stage in an Esaki diode-resistor logic consists of a series arrangement of a diode and a resistor, R , with input and output coupling resistors as shown in Fig. 1. The bias voltage is chosen such that, without any voltage at the far ends of the coupling resistors, it gives rise to a current through the diode which is below the peak current. Consequently, the diode will remain in its low-voltage state. With additional current supplied to the center node through one or more input (or output) resistors, the diode can be made to switch into the highvoltage state. With the bias current only slightly smaller than the peak current, very small "trigger" currents are necessary.