N-Channel LDD Transistor Characterization as a Function of Gate Geometry

The use of LDD (lightly doped drain) devices has allowed transistors to shrink in size while increasing their immunity to hot electron effects. This thesis investigates the effects that gate profiles have on n-channel LDD transistor characteristics. Prior to the use of TaSi sub 2 /polysilicon gates, transistors were formed using rectangular polysilicon gates. However, the definition of the TaSi sub 2/polysilicon gate sandwich can result in three possible gate profiles due to the different etch rates of TaSi sub 2 and polysilicon.