N+/P+ poly gate CMOS process using source/drain implants for poly doping.

N+/P+ poly gate CMOS devices were fabricated using source-drain implants for polysilicon doping and a process modified from the 0.9micron CMOS processing technology. CMOS devices so fabricated show comparable characteristics to devices fabricated by conventional 0.9micron technology. No short channel effects were observed at L sub eff of 0.6micron and 0.5micron for a p and n channels, respectively. The effect of dopant diffusion, both vertical and lateral, was studied in terms of several selected S/D implant anneal temperatures. A S/D anneal at 900C was found to be optimum for the present process. It is shown that an anneal at 950C causes boron penetration from the gate to the silicon, resulting in depletion-mode characteristics in p channels. Lateral diffusion was observed for all processing conditions used.