P8: P4 with Predictable Packet Processing Performance
28 January 2020
As the support of P4 programmability by packet processor is increasing, it is important to identify a relationship between the complexity of the provided P4 pipeline and the packet processing latency.P4 abstracts the processing pipeline of data planes using a limited set of constructs. We analyze the latency costs of these constructs to propose a method that estimates the packet processing latency as a function of the given P4 program. In this paper, we analyze the impact of different P4 constructs on packet processing latency for three state-of-the-art P4 targets: Netronome SmartNIC, NetFPGA-SUME, and T4P4S DPDK-based software switch. Besides comparing the performance of these three targets, we use the derived results to propose a method for estimating the packet latency of P4-based network functions implemented using the surveyed P4 constructs. The proposed method is finally validated using a set of realistic network functions which shows that our method estimates the packet latency with a sub-microsecond error.
