Processing Methods for the Fabrication of Sub-0.25microns GaAs Heterostructure Devices and Circuits

Interest in GaAs Heterostructure FETs has increased significantly in recent years because of the potential benefits in circuit performance over conventional MESFET devices. Short propagation delays have been observed in half micron and sub-half micron logic circuits with little evidence of short channel effects. The purpose of this work was to develop a process for defining sub-half micron gates and to examine the device performance limitations of Heterostructure FETs as gate lengths were decreased below 0.25microns. The methods for reliably defining a half micron lift-off gate have been described previously. A modified lift-off process has been developed in order to define gate features as small as 0.10microns. The gates were produced using a trilevel resist consisting of EBR-9 as the imaging resist. The intermediate level consisted of germanium. PMGI was used as the planarizing resist. For gate lengths below 0.25microns, a JEOL JBX-5DII was used to expose the EBR-9. Exposure doses ranged from 40 to 60 microC/cm sup 2 at 50 keV. The address and spot size were both 250A. Site by site alignment was used to register the gate to the underlying ohmic level.