Stability Analysis of a Parallel Packet Switch with Bufferless Input Demultiplexors
11 June 2001
A class of packet switching systems with inverse multiplexing of switching connections and/or flows (the SCIMUX architecture) has been recently proposed. Such systems open the possibility to use the readily available switch fabrics and port cards in order to build fully-functional packet switches, operating at rates much higher than those of their own components taken in isolation. A comprehensive analytical study of such systems presents a highly demanded piece of information and at the same time remains a largely unexplored research area. In this paper we consider the Parallel packet Switch (PPS) architecture, which is a variation of the SCIMUX architecture with a switching core composed of multiple paralle independent switching planes, restricting our attention to the case of bufferless input demultiplexors.