System Architecture and ASICs for a MIMO 3GPP-HSDPA Receiver

Multiple-input multiple-output (MIMO) technology has been proposed for the high speed downlink packet access (HSDPA) extension in the 3GPP mobile wireless standard [1] to achieve high data throughput with significantly increased spectral efficiency. Data is encoded, interleaved, spread and transmitted over multiple antennas. This paper presents an architecture for a baseband MIMO IISDPA receiver. The architecture is based on two prototype silicon devices that perform MIMO detection (at channel data rates up to 24 Mbps). System simulations prove the high performance potential of the MIMO proposal for HSDPA. Furthermore, the acceptable complexity of both devices demonstrates the practicality of a single chip solution for an HSDPA MIMO receiver.