Temporal alignment of high-speed transmit channels of an FPGA
17 January 2008
We describe a scalable alignment algorithm that corrects for random multiple-bit offsets among parallel transmit data streams of high-speed I/O-ports on an FPGA, as required for subsequent multiplexing or digital-to-analog conversion. We demonstrate the temporal alignment of 17 parallel 10-Gbit/s transmit channels on a Xilinx Virtex II Pro X FPGA.
