The Ballistic Nano-Transistor
01 January 1999
The viability of sub-50nm CMOS technology is contingent upon the drive current performance. Improvements in the drive performance can be used to derate the power supply voltage, thereby improving reliability and reducing power dissipation. The drive performance of a conventional MOSFET is dictated by the thickness of the SiO sub 2 gate dielectric and by carrier scattering in the channel. Since the gate leakage current due to direct tunneling through the oxide renders SiO sub 2 thicknesses less than 1.3 nm impractical, the drain current performance for t sub (ox) >= 1.3 nm is limited by ballistic transport in the channel, which is expected when L sub (eff)