The submicrometer silicon MOSFET.

An overview of MOSFET miniaturization is provided, which is to become Chapter 1 in a book edited by R. K. Watts. The chapter begins by describing the design hierarchy for miniaturization using Warnier-Orr diagrams. Simple models are useful in setting up the hierarchy, and in making it intuitive. Following the outline, the chapter describes downsizing using electrostatic scaling, subthreshold scaling, and rules of thumb for HMOS (high performance MOS) design. The related rules of thumb, a tentative scheme for symmetric CMOS design is proposed that uses off-current as a basic parameter. A survey of some special topics follows: parasitic resistance, transport modeling, hot electron effects, and specific designs for miniaturization, such as the lightly doped drain (LDD), and local interconnection schemes.