Thermal Breakdown of VLSI by ESD Pulses

A three-dimensional thermal model is developed to determine the temperature rise and the voltage build-up of VLSI devices stressed by Human-Body Model (HBM) electrostatic discharges (ESD). Application of the model to a specific device yields failure thresholds and failure sites in agreement with the experimental results. Such a detailed model can be used to evaluate and improve designs of ESD protection circuits. It not only reconfirms the good design principles for ESD protection circuits, but also points out the importance of pulse risetime in determining the failure site.