Timing measurements on MOS VLSI devices driving TTL loads.

Most manufacturers of VLSI test equipment are designing 256- pin test heads with transmission lines leading from the device- under-test (DUT) to driver-comparator circuits that are sometimes 50 cm away. Reflections within the transmission lines can cause serious timing measurement problems with high current, MOS output buffers designed to drive highly capacitive TTL loads. For example, measurements can be in error by as much as 10 ns even though automatic test equipment can be adjusted to subnanosecond accuracy. This paper shows how the ADVICE simulator can be used to analyze the transmission line problems that occur when the Advantest T-3340 system is used to test three classes of output buffer in the WE 32100 microprocessor. It is concluded that corrections must be incorporated in test programs, and capacitors must be added to the outputs of the DUT, to reduce the 10 ns timing errors that would otherwise occur when the DUT is required to drive TTL loads having 130 pF of capacitance. It is also recommended that resistors be added to the outputs of the DUT to prevent the damped transmission line oscillations that occur following logic voltage transmissions with very low impedance buffers. Without the resistors, timing measurements could give highly erroneous or ambiguous results on the order of 20 ns.