Vertical enhancement-mode InP MISFETs fabricated on n-type substrate.
01 January 1986
We report a new vertical structure InP enhancement-mode MISFET. These transistors are made on an Fe-doped semi-insulating InP epitaxial layer grown by organometallic vapor phase epitaxy on an n-type substrate. Thermally evaporated borosilicate is used as the gate insulator. Transconductances as high as 100 mS/mm have been achieved with a gate length of approximately 2.8micron. The novelty and advantages of the vertical structure are discussed.