Abhishek Patil

Biography

Abhishek Patil is a Physical Backend Design Engineer in the Platform and ASIC research team at Nokia Bell Labs. He owns the development of physical design backend flows and drives partition-level execution for advanced designs tailored for network applications. His work bridges the gap between complex architectural concepts and physical silicon realization, enabling high-performance, power-efficient, and structurally sound hardware designs for next-generation communication systems.

Abhishek started his career as a systems administrator at IBM India Pvt Ltd, where he worked for over two years before pivoting into physical design, driven by his interest in silicon architecture and hardware implementation. With over eight years of experience in physical design across cutting-edge technology nodes from 12nm down to 2nm, he has successfully delivered complex designs at AMD, Broadcom, and MediaTek. His work spans a diverse landscape of high-performance semiconductor architectures, including graphics processing units (GPUs), networking chips, system-on-chips (SoCs), and AI accelerators.

His expertise covers the entire synthesis-to-GDSII spectrum, including resolving critical bottleneck issues across complex designs and implementation flows with physical design and automation skills. He brings experience in different types of designs including multi-voltage, macro-dense, and multi-million instance logic designs.

Abhishek received his Bachelor of Engineering (B.E.) in Electronics and Communications from MVJ College of Engineering (affiliated with Visvesvaraya Technological University), Bangalore.

His area of interest includes next-generation physical design implementation methodologies, scalable backend flows, and high-density chip optimization for peak PPA. He is focused on creating advanced silicon solutions needed to power AI, networking, and future communications.