Megharaj Panchal is an SoC Design Engineer at the Platform and ASIC Research Lab, Nokia Bell Labs, where he contributes to physical implementation and hardware-software co-design to accelerate next-generation artificial intelligence and machine learning workloads. His work focuses on bridging the gap between high-performance architectures, energy-efficient computing, and the physical realization of novel future-ready edge system designs.
With over a decade of industry-leading experience in physical design and SoC implementation in organizations like Broadcom, Samsung, Qualcomm & AMD, Megharaj has steered complex silicon designs across deep sub-micron technology nodes ranging from 28nm down to 3nm. His expertise spans the entire RTL-to-GDSII execution spectrum, including high-speed CPU/GPU convergence, multi-voltage power domains, and AI-driven PPA optimization. Throughout his career, he has contributed to the core hardware architectures powering advanced mobile processors, high-performance discrete GPUs, and future-ready edge systems.
Megharaj holds a B.E. in Electronics and Communication Engineering from BLDEA’s CET, Bijapur/Vijayapura (affiliated with Visvesvaraya Technological University, Karnataka). His ongoing professional focus lies in building the highly optimized, energy-efficient physical silicon—harnessing advanced sub-3nm nodes and co-design methodologies—that will power tomorrow’s intelligent communication systems.
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