Savitha Mayuranathan is a SOC Frontend design engineer at Nokia Bell Labs working on AI accelerator SoC implementation, with current responsibilities spanning Memory RTL integration and Verification, Physical synthesis, Pre- and Post-layout timing analysis, Conformal verification, and UPF development and timing constraints for synthesis and signoff flows. Her work is centred on enabling high-quality implementation for advanced-node designs through strong alignment between RTL, architecture, and physical design objectives.
Before joining Nokia Bell Labs, she held technical roles at Qualcomm, Synopsys, and IBM, where her work covered synthesis, Floor planning, Placement and route, Static Timing Analysis, Formal Verification, ECO execution, and signoff activities across multiple technology nodes from 22nm to 2nm. She brings strong expertise in end-to-end implementation flows and methodology development, backed by hands-on proficiency in Fusion Compiler, Genus, Innovus, Primetime, Tempus, Conformal, and related verification and signoff tools. Over the course of these roles, she contributed to implementation methodology development for Mobile, XR, automotive, and server-class ASICs, while also supporting customer-facing EDA enablement and quality-of-results improvement initiatives.
She earned her B.E. in Electronics and Communication Engineering from Madras Institute of Technology, Chennai. Her work has been recognized through several awards for technical impact excellence, design impact, and execution on complex product programs.
Biography
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