Sequentially Companded Modulation for Low-Clock-Rate Speech Codec Applications

The many distinct advantages of companding to encompass the dynamic range of speech signals are well documented. In most cases, a simple law is used repeatedly to arrive at the companded step size. For instance, in the 37.7 kHz, ADM SLC-40 codec,1 a nonlinear function of the frequency of occurrence of four identical consecutive bits forces an expansion of the step size. In the two-bit companding described in Ref. 2, the expansion of step size follows a geometric progression. Three bit companding described in Ref. 3, again depends on a base-two geometric series for increasing the step size, when two consecutive bits are the same, and again on the same series with a base-half for decreasing the step size when the bits are of opposite polarity. Most of these systems perform adequately at higher (typically above 32 kHz) clock rates. However, when the clock rate is decreased, the simple fixed rules of companding either offer an unacceptable quantization noise at lower step sizes, or make the 765