Abhishek Kalkeri

Biography

Abhishek Kalkeri is a Physical Backend Design Engineer in the Platform and ASIC Research team at Nokia Bell Labs, contributing to the development of next-generation physical design methodologies and backend implementation. He leads partition and full-chip level execution for advanced AI accelerators, primarily targeting networking and communication applications. His work centers on transforming complex architectural concepts into silicon, enabling high-performance, power-efficient, and physically optimized hardware solutions for next-generation communication systems. 

With nearly nine years of specialized experience in Physical Backend Design, he has worked across a wide range of advanced semiconductor technology nodes, spanning from 16nm to leading-edge 2nm processes. Throughout his career, he has played a key role in the successful delivery of several high-performance products, including server processors, CPU and GPU platforms, and AI accelerators. His expertise covers the entire physical implementation lifecycle, including floor planning, place-and-route (PnR), timing and physical closure, power optimization, and signoff methodologies. He possesses extensive experience in driving complex, multi-million-gate designs characterized by high density, challenging congestion profiles, and aggressive performance targets. His technical depth, combined with a strong understanding of advanced implementation methodologies, has enabled the successful execution of highly demanding semiconductor projects across multiple technology generations.

Abhishek has completed his Master's degree in Microelectronics & Controls Systems from PES Institute of Technology [affiliated to Visvesvaraya Technological University], Bangalore. Prior to joining Nokia Bell Labs, he has built a strong record of technical execution across leading semiconductor organizations and engineering teams including Intel, Broadcom and AMD. In addition to delivering complex physical design partitions, he has experience in leading teams across multiple partitions, driving successful execution through effective coordination, technical expertise, and strong project management.

His research interests include developing next-generation physical design methodologies, advancing backend implementation flows for improved scalability and efficiency, and optimizing high-density chip designs to achieve superior Power, Performance, and Area (PPA) outcomes. He is particularly passionate about enabling innovative silicon solutions that address the growing computational demands of AI, networking, and future communication technologies.