Modern integrated circuits can contain transistors smaller than 100 nm and gate oxides as thin as 2 nm.
The excessive gate leakage current of the planar- and mesa-type InAlN/GaN heterostructure field-effect transistors (HFETs) is evaluated.
We have fabricated In sub (0.52) Al sub (0.48) As/In sub (0.
Frequency dividers and ring oscillators have been fabricated with submicron gates on selectively doped AlGaAs/GaAs heterostructure wafers.
An integrated set of gate matrix tools was developed for the physical implementation of GaAs IC circuits to demonstrate the capabilities of a new LSI GaAs pilot production line, partially supported
As the silicon industry moves forward, smaller devices with lower operating voltage and thinner gate oxides are being manufactured.
We demonstrate that reliability projections can be improved significantly if oxide thickness uniformity is improved.
The present study, improving on a earlier effort, experimentally evaluates the pressure drop through gates of varying width, depth, and length, and converging angle.
This article has been prepared as an invited paper for Symposium J at the 1999 MRS fall meeting, Advanced Materials and Techniques for Nanolithography.
We report on progress and gate technology issues in scaling both NMOS and PMOS conventional planar transistors to a physical gate length of 30nm and an expected effective channel length of 10 nm.
