The memory system associated with the 3B20D Processor 1 includes a 16-megabyte memory, a high-speed cache memory, and hardware assistance for the virtual-to-physical address translation process, ac
Many of the diagnostic principles and features embodied in the 1A Processor 1 have been incorporated in the maintenance design for the 3B20D Processor.
This article describes the design of the DMERT operating system nucleus.
The 3B20D Processor has extensive maintenance subsystems associated with it and is designed to meet the high-availability standards of Bell System electronic switching systems.
An integral part of high-reliability applications of the Duplex Multiple Environment Real Time (DMERT) operating system is the administration of system hardware information and of software.
An important aspect of the development of any complex system such as the 3B20D Processor is the methodical integration and system testing during all phases of the development consistent with the ex
The 3B20D Processor is the first member of a family of processors designed for a broad range of Bell System applications.
The direct predecessor of the 3B20D, the 3A Processor, included a real-time monitor known as the Extended Operating System (EOS).
Copyright © 1983 American Telephone and Telegraph Company. Printed in U.S.A. The 3B20D Processor & DMERT Operating System: Prologue By J. M.
The software that comprises the operating system, diagnostics and fault recovery, configuration data base, field utilities, and craft interface for the 3B20D Processor has been undergoing developme
