The neural network, implemented in CMOS technology, contains 256 'neurons', each with 128 binary, programmable connections.
The large interconnectivity and the moderate precision required in neural network models present new opportunities for analog computing.
This paper describes the analog front end of a two-chip U-interface transceiver based on the American National Standard Institute (ANSI) 2B1Q line code.
A 12MHz 760mW analog front end for DMT-based VDSL integrates all active components except line driver in a single BiCMOS 0.35μm ASIC.
In this paper, we present an experimental link performance analysis of mode-locked laser based radio-over fiber systems operating in the millimeter-wave range around 60 GHz.
We have used an integrated narrowband optical filter fabricated in 0.18 micron CMOS process to optically slice a modulated broadband RF signal into an individual channel of 1 GHz bandwidth.
Analog Scramblers for Speech Based on Sequential Permutations in Time and Frequency By N. S. JAYANT, R. V. COX, B. J. McDERMOTT, and A. M.
A real-time analogue multiplier uses two impedance bridges in cascade, each unbalanced to an extent dependent on one of the quantities to be multiplied.
Analog simulation of physical systems governed by partial differential equations is a well known technique in many disciplines, notably fluid mechanics and aerodynamics where wind tunnel testing is
The application of turbo codes in modern communication systems makes decoding a time and power consuming task.
