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    A 0.5μ CMOS Low-distortion Low-power Line Driver With Embedded Digital Adaptive Bias Algorithm For Integrated ADSL Analog Front-ends

A 0.5μ CMOS low-distortion low-power line driver with embedded digital adaptive bias algorithm for integrated ADSL analog front-ends

01 January 2002

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A 5V 0.5μm CMOS line driver has distortion -65dB in the ADSL upstream band for a 4V peak-to-peak differential output swing on a 12.5Ω load. The quiescent current is controlled digitally with a dedicated algorithm that corrects for offsets and process variations. The driver is integrated in a complete ADSL CPE analog front-end

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