Enabling Shallow Trench Isolation for 0.1 micron Technologies and Beyond

Shallow trench isolation (STI) has become the standard isolation structure for sub-micron silicon CMOS technologies. However, following the trend of device scaling, the isolation for future generations will have minimum width of about 130nm for 0.1 micron technologies for 100nm for 0.07 micron technologies. It is highly desirable to extend the current STI structure, widely adapted in manufacturing, to those dimensions, but many issues become difficult to resolve. In this work we will show that with a novel enabler--high temperature re-oxidation (HTR) for corner rounding and by properly addressing the issues of trench fill, corner profiles, tub implants, channel width loss, reverse narrow channel effect (RNCE), defect density and junction leakage, the basic STI structure can be extended to 0.1 micron and beyond.