Fabrication of Reduced Area InGaAs/InP HBT and DHBT Devices

We have developed a robust fabrication procedure for reduced area InP based HBT's, using a process involving both wet etching and ECR plasma etching. Device parameters, such as the gain, R sub e, R sub b, R sub c, and C sub (bc) were evaluated as a function the base layer width and device geometry to optimize the layer structure. In addition, the microwave characteristics of both single and double heterojunction bipolar transistor devices were evaluated. This process is presently being implemented for the fabrication of high-speed integrated circuits.