Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits

The challenge of testing silicon integrated circuits (iCs) is becoming more formidable with the rapidly expanding production of large-scale integrated (LSI) circuits. Increased gate-count, increased pin-count, smaller feature size, higher performance, and higher complexity all contribute to a mounting "testability" problem. Furthermore, there is considerable evidence that the economic requirements to meet that challenge will continue to grow at a rate markedly greater than that of circuit size alone. As a further dimension to the challenge, IC tests must be specifically designed to recognize failure-mode dependence upon circuit configuration, processing parameters, and the overall technology (TTL, ECL, PMOS, CMOS, etc.). That is, a Boolean network realized in one technology can have a strikingly different implementation in another. Consequently, logic tests must be created which exercise not only the gross functional behavior of the IC but also the structure used for that function. However, for large-scale ICs, internal circuit structure and complexity are in1449