Floor Planning Using Simulated Annealing

This paper presents an application of the simulated annealing method to floor planning in VLSI Layout. The problem is to optimally pack a given set of modules in such a way as to minimize the chip area and also to minimize the interconnect. The program has the problem of selecting the most optimal aspect ratio for each module out of the possibilities specified. We limit ourselves to slicing structures and use a reverse polish notation to represent these. Facilities have been designed to consider signal priorities, hard-placed cells and input-output buffers.