High K Dielectrics for Giga-Scale CMOS and Non-Volatile Memory Technology

The scalability of MOS/CMOS devices and giga-scale integrated of silicon can be primarily attributed to the fact that silicon has a native gate dielectric SiO sub 2 which has been hyper-scaled from ~200nm to 2-3nm in manufacturing. With SiO sub 2 facing a fundamental limit at ~0.7nm and perhaps practical limit at ~1.2-~1.5nm, the CMOS industry beyond 70nm faces a challenge to replace SiO sub 2 with a high-K dielectric constant material. Also, the high density embedded non-bolatile memory industry faces a challenge to come up with low voltage high speed Flash or high density ferroelectric technology. In this talk, we will benchmark SiO sub 2, Si sub 3 N sub 4, Al sub 2 O sub 3 and Ta sub 2 O sub 5 for FETs and Flash technology.