High-Speed VLSI Implementation of Reduced Complexity Sequence Estimation Algorithms with Applications to Gigabit Ethernet 1000 Base-T

In the past, various reduced complexity sequence estimation algorithms (RCSE) have been reported. However, literature on the high-speed VLSI implementation of RCSE, which is non-trivial because of its hardware cost and long critical path, is rare. This paper compares known RCSEs in terms of performance, VLSI implementation, hardware complexity and critical path. A novel architecture is presented which reduces the complexity for RCSE and relaxes the critical path problem. This architecture can be used to implement RCSE for Gigabit Ethernet 1000Base-T.