How to Meet the Packaging/Assembly Challenges

The new qualification/certification procedures for chip design, wafer fab, and packaging/assembly place the emphasis on in-line control as opposed to the present final product testing. The specific challenges in the packaging/assembly areas are the increasingly higher electrical, thermal, and mechanical performance requirements, the wide variety of package types and designs (DIP's), PGA's, LCC's), the high number of leads (I/O's), the small quantities produced and the new PWB assembly processes.