Image Processing Performance Evaluation for DSP Based Parallel Computers with Distributed Frame Buffer
03 April 1990
The computational power and the instruction repertoire of the floating point digital signal processors (DSP's) have reached a level that makes it possible to build DSP based parallel computers for high resolution image processing (IP) applications. At the current state of the technology a very large number of DSP's can be used in such a machine and this makes the architecture the main performance determining factor.