Image Processing Performance Evaluation for DSP Based Parallel Computers with Distributed Frame Buffers

Digital signal processor based parallel computers using distributed frame buffers constitute an important class of digital image processing machines. There are a large number of possible architectures for these type of computers and because of the nonexistence of a unified computational model for image processing, selection of the most appropriate architecture becomes a problem. As a guideline for architecture selection, this paper presents performance evaluation criteria based on a small set of basic tasks common to majority of image processing applications. The criteria can also be used as a basis to construct a computational model for image processing on this type of computers.