Impact of Interconnect Architecture on Chip Size and Die Yield

Interconnecting 200 million transistors in high performance logic circuit requires several kilometers of wires at the 100 nm technology node for which volume production is only seven years away. In order to reduce the interconnect RC delay the interconnect pitches need to be larger than minimum scaling except for the lowest levels, even when Cu and low K dielectric are used. The larger pitches result in increased die size and/or more levels of interconnects, both adversely affect die yield. This work quantifies the impact on die yield for various interconnect approaches.