Implementation and Bench Characterization of a Read Channel With Parity Check Postprocessor

We report here the implementation and characterization of a parity check postprocessor which can operate using a single parity bit on a user data block size of 4 or 6 bytes, or using 4 parity bits on a user data block size of 12 bytes. Two performance criteria are considered: byte error rate, and ECC overload (retry) rate. A simple model for byte errors on an interleave similar to [1] is proposed which allows for the prediction of retry rate from reasonably sized sets of data generated on the bench or in simulation. Unlike models which attempt to study error burst statistics [2][3], this model does not need to assume that the burst error statistics are invariant with respect to BER - an assumption which is in general not true for any of the new class of large block parity based detectors.