Interconnect Synthesis without Wire Tapering

Interconnect synthesis techniques such as wire sizing and buffer insertion/sizing have proven to be critical for reducing interconnect delays in deep submicron design. Consequently, the past few years have seen several works which study buffer insertion, wire sizing, and their simultaneous optimization. For long interconnect, wire tapering, i.e., reducing the wire width as the distance from the driver increases, can yield better solutions than uniform wire sizing. However, despite its obvious benefits, tapering is not widely used in practice since it is difficult to integrate into a coherent routing methodology. This work studies the benefits of wire sizing with tapering when combined with buffer insertion.