Isolation's path to SOI technology

While CMOS silicon-on-insulator clearly results in improvements in device physics and electrical parasitics, its application has to address issues associated with using this material substrate, including changes, although minor, to several wafer fabrication processes and modified CAD tools. Manufacturers pursuing this route need to ask: Are the added R&D costs and the overall improvement in performance cost effective compared to standard bulk-silicon or epitaxial-based VLSI CMOS technology? The answer is rather complex and is intimately linked to the final IC. The technology of choice will be the one that provides the desired function at the lowest cost.