LAMP: Logic-Circuit Simulators

The use of digital simulation of logic circuits has been widely accepted in the computer and telephone industries to verify logiccircuit designs, to analyze the behavior of logic circuits in the presence of faults (such as gate outputs permanently stuck at logical 0 or logical 1, open gate inputs and shorted gate outputs), and to aid the generation of fault-detection tests for logic circuits. Most simulators described in the literature can be divided into three categories. T h e first category includes the true-value simulators t h a t simulate the circuit in the absence of any faults or, by altering the circuit description, simulate the circuit in the presence of one permanent fault. 1 , 2 The second category includes the parallel simulators t h a t c o n c u r r e n t ^ simulate the fault-free circuit and the effect on the circuit of a small set of single permanent faults. 2 - 4 T h e third category includes the deductive simulators t h a t concurrently simulate the fault1451 free circuit and the effect on the circuit of all single permanent faults. 5 The Logic Analyzer for Maintenance Planning (LAMP) system contains simulators from each category. The L A M P system has been extensively used over the last four years to simulate the No. 1A and No. 4 Electronic Switching Systems to verify the logic design, to aid the generation of diagnostic tests, and to analyze the behavior of the circuits in the presence of faults. Circuits containing 52,000 gates and 23,000 single faults have been simulated using the I B M 370 Model 168 as the host machine.