Linear MIMO Equalization for High-Speed Chip-to-Chip Communication

In this contribution, we present a linear multiple-input multiple-output (MIMO) equalization scheme at the receiver side for high-speed electrical chip-to-chip communication. As opposed to traditional single-input single-output (SISO) equalization per lane, this MIMO approach enables cooperating receivers to treat crosstalk (XT) between neighboring channels as an information-bearing signal instead of a disturbing signal, allowing to mitigate both inter symbol interference and XT. Given a 4 X4 MIMO channel obtained from measurements on an actual electrical chip-to-chip interconnect, we point out that, for a given total number of equalizer taps, MIMO equalization can outperform SISO equalization. For instance, when operating at 50 Gbit/s and using an oversampling factor of 2, MIMO equalization with a total of 112 taps (i.e., 7 taps per individual filter) has a power advantage of about 0.53 dB at a BER of 10^-12 compared to SISO equalization with 116 taps (i.e., 29 taps per individual filter).