Logic modeling in the MARS accelerator.

MARS (Microprogrammed Accelerator for Rapid Simulations) is an exploratory hardware accelerator which has been microcoded to implement two logic simulators, namely, unit and multiple delay simulators. This memorandum describes a circuit compiler, MCC (MARS Circuit Compiler) that produces the MARS data structure for circuits described in LSL for Motis3 and Advice descriptions that have been compiled through Motis3 preprocessors. The transformation of circuits into four-input gate structure for MARS is automatic. Special models for transmission gates and buses are also incorporated in MCC which derives much of its strength from HASTEN3, a production tool in Area 52 for accessing the Zycad accelerator.