Low Power Nonlinear MIN/MAX Filters Implemented in the CMOS Technology

A novel current-mode, binary-tree, asyn- chronous, nonlinear Min/Max lter is presented. In the proposed circuit an input signal (current in this case) is rst sampled in a circular delay line, controlled by a mul- tiphase clock. In the next stage particular samples are converted to 1-bit signals with delays proportional to the values of these samples. In the following step the delay times are compared in digital binary-tree structure. The circuit has been simulated in the TSMC CMOS 0.18 m technology. It offers a precision of 99.5% at data rate of 2.5 MSamples/s and energy of 0.3 { 1 pJ per input.