Low-Power, Small-Footprint Gigabit-Ethernet-Compatible Optical Receiver Circuit in 0.25 micron CMOS

We present experimental results for a photo-receiver circuit capable of operating with gigabit Ethernet signals and generating full CMOS logic levels. A dc-coupled single-ended pre-amplifier is coupled with an averaging capacitor to a differential post-amplifier that uses inverse scaling to increase bandwidth. The circuits are realized in 0.25 micron CMOS, dissipating 26 mW or less. The analog portion of the receiver requires as little as 2 micro-amps average input current at 1.25 Gb/s, increasing to about 10 micro-amps when CMOS levels are generated. The analog portion exhibits a maximum operating speed of 2.1 Gb/s. To our knowledge, this is the fastest CMOS photo-receiver circuit yet realized at this dissipation level capable of full CMOS levels.